Optimal chip sizing for multi-chip modules

The functions of a complex electronic system will be partitioned across multiple chips. An optimal system using PWB technology will contain just a few chips in order to minimize the inter-chip delays. However, the area delay penalty for inter-die interconnects is much lower for MCM technology, and different partitioning options should be considered. This paper develops a criteria for optimal MCM chip sizing based upon system quality level, cost and silicon efficiency. The criteria are then applied to a 500,000 gate MCM case study.<
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