A monolithic processing subsystem

A single-chip 120 MFLOP (peak) 26 million transistor digital processing subsystem with 512 kilobytes of on-chip SRAM has been developed. This general purpose 32-bit floating point Harvard architecture device, which incorporates sophisticated communication capabilities and at maximum throughput dissipates less than 2 W, can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arrays. This paper describes physical and functional features of the chip, and provides some discussion of how it can be applied.<
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