Optimization of series resistance in sub-0.2 μm SOI MOSFET's

The optimization of device series resistance in ultrathin film SOI devices is studied through 3-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 μm, thin-film SOI devices with excellent performance and very low device series resistance.