A digital filter chip for ECG signal processing

A VLSI implementation of a linear-phase digital filter for ECG signal processing has been designed. With a sampling rate of 100 Hz, the passband is from 0.5 Hz to 49.5 Hz with 0.5-dB ripple. The filter architecture is based on the use of recursive running-sum blocks, resulting in a very low computational complexity. Module generators have been used in the layout design for high integration density. The circuit has been designed for a 2.0-/spl mu/m double-metal CMOS technology, having about 34000 transistors and a 15.43-mm/sup 2/ chip area.<
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