New CMOS shallow junction well FET structure (CMOS-SJET) for low power-supply voltage

A novel CMOS device structure called as CMOS shallow junction well FET (CMOS-SJET) has been proposed for high speed operation at low power-supply voltage. Since well regions underneath the channel regions of both n-channel and p-channel MOSFETs in the CMOS-SJET are fully depleted, steeper subthreshold characteristics can be achieved. Furthermore, junction capacitances are reduced by half compared with those of the conventional CMOS structure. Therefore the gate delay of 52 psec/stage at 1.5 V operation and low power-delay product of 1 fJ are verified with 0.35 mu m gate length design. The CMOS-SJET structure appears to offer high performance with low power-delay product at low voltage operation.<>