Dual (n/sup +//p/sup +/) polycide interconnect technology using poly-Si/WSi2/poly-Si structure and post B/sup +/ implantation

Formation of low resistance p/sup +/ contact was the most difficult problem for dual(n/sup +//p/sup +/) polycide interconnect by which both n/sup +/ contacts and p/sup +/ contacts are directly connected. To solve this problem, we have developed a new technology with a sandwiched poly-Si/WSi2/poly-Si structure, and a post B/sup +/ implantation over the entire polycide including both p/sup +/ and n/sup +/ regions. As a result, this new technology provides sufficiently low resistance for both p/sup +/ and n/sup +/ contacts independent of the spacing distance between p/sup +/ and n/sup +/ regions even after 900 degrees C annealing for 90 minutes and the compact layout of CMOS circuit is made possible while maintaining compatibility with conventional high temperature processes including the economical BPSG flow.<
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