A low power 0.25 mu m CMOS technology

A 0.25 mu m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi/sub 2/ salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.<
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