Integration of power LDMOS into a low-voltage 0.5 mu m BiCMOS technology

Integration of a power Lateral Double Diffused MOS (LDMOS) structure into a high performance 0.5 mu m BiCMOS technology for high density, multi-functional integrated circuit (IC) applications is described. The advantages of VLSI processing and rules have been applied to the design and the manufacturing of the high density LDMOS without sacrificing the performance of 0.5 mu m dual-poly (n/sup +//p/sup +/) gate CMOS and polysilicon emitter bipolar (f/sub T/=26 GHz) transistors. The measured source to drain on-state resistance of the fabricated LDMOS is 90 m Omega -mm/sup 2/. Further device optimization, by means of 2D numerical simulations, can increase the breakdown voltage of the LDMOS to 60 V using this technology.<
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