Code generation for a DSP processor

Proposes a method for compiling an application program into microcodes of a programmable DSP processor. Since most state-of-the-art DSP processors feature some sort of parallel processing architectures, the code generation is a non-trivial task. Based on several scheduling and allocation techniques previously developed by the CAD community for high-level synthesis, we propose a DSP code generator. We emphasize reducing the memory access and register usage conflicts, which often lengthen the total execution time. Starting with an as-soon-as-possible scheduling, without regard to the resource constraints, we transform this illegal scheduling step-by-step into a legal one. In the meantime, registers are allocated and reallocated for variables, taking into account both memory access and register usage constraints. A software system called THEDA.DSP/sub CG/ has been implemented and tested using a set of benchmark programs. Simulation of generated codes which are targeted towards the TI TMS320C40 DSP processor shows that the proposed approach is indeed very effective.<
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