Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates

The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-H Omega process was executed. MOSFET behavior was then evaluated.<
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