A preprocessing architecture for resolution enhancement in high-speed analog-to-digital converters

High performance analog-to-digital converters (ADC's) employ a parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high speed comparators (analog preprocessing). This paper identifies a new preprocessing approach that can be easily incorporated into the established techniques to provide an enhanced resolution capability with fewer number of comparators loaded in parallel. The approach is based on preprocessing the analog signal with a symmetrical number system (SNS). The SNS preprocessing is used to decompose the analog amplitude analyzer operation into a number of sub-operations (moduli) which are of smaller computational complexity. Each sub-operation symmetrically folds the analog signal with folding period equal to the moduli. Thus, each sub-operation only requires a precision in accordance with that modulus. A much higher resolution is achieved after the N different SNS moduli are used and the results of these low precision sub-operations are recombined. By incorporating the SNS folding concept, the dynamic range of a specific configuration of folding periods and comparator arrangements can be analyzed exactly.<
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