Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N/sub 2/O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 /spl Aring/) and five N/sub 2/O anneal conditions (900/spl sim/950/spl deg/C, 5/spl sim/40 min) plus nonnitrided process and channel lengths from 0.2 to 2 /spl mu/m were studied to establish the correlation between the nitrogen concentration at Si/SiO/sub 2/ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N/sub 2/O anneal step can increase CMOSFET's lifetime by 4/spl sim/10 times, effectively suppress boron penetration from the P/sup +/ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO/sub 2/ interface. The optimal N/sub 2/O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO/sub 2/ interface which can be realized by annealing 60/spl sim/110 /spl Aring/ oxides at 950/spl deg/C for 5 min or 900/spl deg/C for 20 min.<
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