A DMOSFET having a cell array field ring for improving avalanche capability

A DMOSFET having a cell array field ring for improving avalanche capability is described. When shrinking the cell size of the DMOSFET, the cell array field ring is effective for unifying the power dissipation over the chip surface during avalanche breakdown. The power dissipation of this durable DMOSFET is uniform over the chip surface during avalanche breakdown. Its avalanche failure power is around 127 W/mm/sup 2/ for a 1-ms pulse width and tends toward a tau /sup -1/2/ dependence. A failure mechanism during avalanche breakdown is also studied. The critical failure temperature of this DMOSFET is only 50 K lower than the intrinsic temperature for the N-drain regions.<
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