An analytical approach to floorplanning for hierarchical building blocks layout (VLSI)

An analytical approach for the floorplanning of rectangular blocks with constraints on their connection and dimensions that minimize the wire length and area is described. The approach consist of two phases: relative placement places the building blocks in a plane so that the topology of the blocks satisfies the combined goal of short interconnection and small bounding area for a given aspect of ratio. The spacing phase removes the overlap in the floorplan resulting from relative placement by moving and reshaping the blocks. Both phases are modeled heuristically as unconstrained minimization problems. The constraint on the shape of floorplan is met by using a bounding penalty function. Indirect connections between large blocks are taken into account for more efficient area utilization. The floorplanning algorithm has been implemented and shown to be effective for handling floorplanning under various kinds of constraints.<
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