Performance and reliability evaluation of high dielectric LDD spacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G/sub M/ and total gate capacitance, C/sub GG/. For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C/sub GG/ has significant impact on the AC performance. The increase of C/sub GG/ due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N/sup -/ source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N/sup -/ doses. The optimized N/sup -/ dose designed for hot carrier reliability issue (under V/sub GS/-V/sub T/=0.5 V/sub DS/ operation) is located around 2/spl times/10/sup 13/ cm/sup -2/ for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N/sup -/ dose condition.<
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