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Yield enhancement in the routing phase of integrated circuit layout synthesis | IEEE Conference Publication | IEEE Xplore

Yield enhancement in the routing phase of integrated circuit layout synthesis


Abstract:

An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduc...Show More

Abstract:

An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms.<>
Date of Conference: 19-21 January 1994
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-1850-1
Conference Location: San Francisco, CA, USA

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