High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-/spl mu/m photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/. An extremely high input sensitivity of 15 mV/sub p-p/ and a wide phase margin of 260/spl deg/ at 10 Gb/s are achieved.<
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