A broadband ISDN line termination chip set for 1.2 Gb/s

A broadband ISDN (integrated services digital network) line transmission chip for 1.2 Gb/s is described. Two technologies are employed: BiCMOS to handle 622-Mb/s off-board interfaces, and CMOS to handle the high-complexity functions. Throughout the system, data are transmitted at a logical rate of 622 Mb/s. In CMOS, this is realized over four parallel 155-Mb/s links, while in BiCMOS, it is realized over a single 622 Mb/s link. The CMOS chips are interconnected through homochronous links operating at 155 MHz. Each chip has about 1-M transistors operating at clock speeds of 40 to 155 MHz. Since the phase of the 155-Mb/s data is unknown, bit synchronization is required at the receiving side. A tunable delay line approach to bit synchronization was chosen. The eye diagram at the 155-Mb/s CML (common mode logic) interface is shown.<
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