The efficient implementation and analysis of a hybrid number system processor

A hybrid number system processor designed with the antilogarithm programmable logic array (PLA) is described. In the hybrid number system, linear interpolation is used to achieve accurate conversions between floating-point (FLP) and logarithmic number system (LNS) numbers. Originally, a multiplier was used to do the interpolation. Here, the antilogarithm PLA is shown to have smaller silicon area, comparable overall performance, and structured design. The basic arithmetic operations and processor architecture are explained for performing addition, subtraction, multiplication, division, and square root. The conversion errors are analyzed mathematically. The Taylor series approximation is used as the framework for analysis of the conversion errors of logarithm, antilogarithm, multiplication/division, and addition/subtraction operations. The analyses indicate that the Taylor series truncation results in very small error when the ROM size is properly chosen for the desired precision. Consequently, the finite width truncation becomes the major source of conversion errors.<
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