Multifrequency zero-jitter delay-locked loop

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions.<
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