A VLSI architecture for automatic speech recognition on large vocabularies

The VLSI architecture of a coprocessor for automatic speech recognition is presented. The processor is capable of executing the most computationally intensive task in speech recognition, the Viterbi-search for word- and sentence-hypotheses, in real-time. This is achieved by a specialized arithmetic unit (AU) and an application specific memory architecture. The arithmetic core attains a clock frequency of more than 50 MHz and consists of 14000 transistors. The memory architecture excels by a highly parallelized memory access enabled by three independent address units and a memory bandwidth of 266 MByte/s.<
>