Testing gate-to-channel shorts in BiCMOS logic gates

The effects of gate to channel breakdown on the operation of BiCMOS logic gates are described. Both the static and dynamic behaviors of the gates are examined. The results of a SPICE simulation are presented. They show that gate to channel breakdown cannot be modeled by a stuck-at fault. I/sub ddq/ and delay testings are effective in detecting these defects. Test patterns for I/sub ddq/ are given.<
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