A methodology for automated behavioral verification of floating-point designs

Behavioral verification of hardware designs confirms that the input/output relationship of the circuit agrees with its specification. This involves simulations of the circuits and the software code that models the hardware. Key issues in such simulations are the generation of test vectors and creation of models. A methodology that automates behavioral verification of floating-point (fp) designs is described. Tools developed to generate test vectors (vecgen) and the models (fpc) and their roles in the verification process are discussed. The methodology has been used successfully on a large number of fp designs over a short period of time.<
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