A VLSI motion estimator for video image compression

The authors present a VLSI motion estimator based on the full-search block-matching algorithm (FSBMA) for video image compression. To improve the performance, a novel two-dimensional SIMD-systolic architecture has been derived. Currently, based on a 0.8 mu m CMOS technology, a VLSI chip has been implemented and fabricated for such an architecture. The chip is functionally correct and packaged as a 68-pin PGA chip. With such a chip, the motion vector of each 16*16 block can be generated in 1252 cycles (i.e., 54.4 mu s for 23 MHz systems). Therefore, even with a small pin-count, a high-performance FSBMA-based motion estimator can still be developed.<
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