VLSI chip set for 2D HDTV subband filtering with on-chip line memories

A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450 000 transistors on 92 mm/sup 2/.<
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