Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor

Two pseudo-concurrent fault diagnostic approaches, namely, a roving spare technique and an inverse residue checking technique, and a testing strategy for processing elements in a high-speed signal processing system, are studied. The system consists of an array of identical (differing only in programmable coefficients) chips that perform complex arithmetic operations. Expressions for fault coverage and average fault latency using random tests for the two diagnostic techniques are obtained. A tradeoff between hardware overhead and average fault latency is identified. A comparison of the two techniques with respect to a set of attributes is presented. The fault-diagnostic techniques described were found to be suitable for implementation on a generalized-sidelobe-cancellor architecture mainly because of the memoryless property of the computations.<
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