On the implementation of a parallel algorithm for higher radix division

A general approach is outlined for designing units for higher radix division, which are based on two subunits operating in parallel. A lower radix division unit is used as the building block of the architecture, and the division step is split into two phases which are carried out in parallel. It is shown that the proposed architecture permits the design of units for higher radix division with digit selection tables requiring few supplementary input bits compared to the tables used by lower radix division systems.<
>