The high level design of a chip for scientific computation

An architecture and its high-level description of a chip suited for the exact calculation of inner products are discussed. A highly parallel implementation is developed using eight independent adder stations, which add products to two circular long accumulators. A dispatcher schedules each product to the best available station. To validate this architecture and to calculate its performance, a high-level description is created. This description is made with ESCHER +, a schematic entry tool with a built-in simulator. This tool can be used to interactively develop and simulate a high-level description. Animation is used to validate the communication between the different modules of the architecture. The resulting description showed its ability to be the basis for the further implementation of the chip.<
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