The MIPS M2000 system

The M2000 represents an attempt to design a system optimized to support a RISC (reduced-instruction-set computer) processor. While RISC processors in general have a high memory-bandwidth requirement, the R3000 through the use of data block refill, instruction streaming, and write streaming has been tuned to require yet more bandwidth. This tuning is reflected in its 1.25 average cycles per instruction. The M2000 attacks the memory-bandwidth problem by extensive use of page-mode DRAMs (dynamic random-access memory) for all memory accesses: processor reads, processor writes, I/O reads, and I/O writes, using page-mode access. Where a bandwidth mismatch is present, i.e. between the I/O bus and the memory array. FIFO (first-in, first out) buffering is provided to prevent memory tieup.<
>