System architecture and key components for an 8 bit/1 GHz GaAs MESFET ADC

Different ADC (analog-to-digital converter) algorithms were investigated to find an architecture suited for high speed/high resolution converters based on MESFET technologies. A two-stage cascaded converter was selected for achieving 8-b resolution at a 1-GHz sampling rate. Key components for this kind of converter were developed, fabricated, and characterized. Measurements of the track and hold circuitry showed a droop of 3 mV/ mu s, a slew rate of 3 kV/ mu s, and a setting time of 220 ps. Its accuracy corresponds to 9.5 b at a 1-GHz clock rate with a 100-MHz input frequency. The 4-b quantizer operates up to 1.5 GSps. At 800 MSps, 3.8 effective bits were achieved with input frequencies up to 200 MHz. The digital-to-analog converter necessary to reconstruct the analog signal after coarse quantization was merged into this quantizer to minimize the propagation delay of this path, which determines the maximum sampling rate.<
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