Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

A large lattice mismatch occurs when lightly boron doped (E15 cm/sup -3/) epitaxial silicon layers are deposited on a heavily boron doped (E19 cm/sup -3/) substrate. The misfit stress causes wafer bow and the formation of misfit dislocations at the interface. The structure of misfit dislocation and effect of misfit stress on p/p+ wafer processing are discussed. A method for elimination of the misfit stress in p/p+ silicon wafers via lattice compensation is presented.<
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