High-density ASICs with a three-dimensional CMOS process

A vertically integrated process is presented which yields common circuit elements like inverter, selector, exclusive OR and NAND gates for the realization of high-density ASICs. The vertical stacking of up to three channels in bulk-equivalent silicon material permits gains in integration density and suppresses parasitic devices like bipolar latchup and junction capacitances. Improvements in the dual-gate device modelling makes simulations of circuits containing this superior device possible. Through the use of the substrate for ground-supply, the noise immunity is improved and the wiring complexity is reduced. By using process specific interconnection possibilities and the high number of interconnection layers, the increased wiring-area to transistor-area ratio is reduced. This leads to high-density 3D-CMOS ASICs even with relaxed design rules.<
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