VHDL for high speed desktop video ICs-experience with replacement of other simulator

A simulation methodology used for high-speed digital video processing IC development is described. The simulation environment is optimized to meet application-specific requirements for the efficient hierarchical mixed-level simulation of large stimuli sets. To increase design efficiency, the simulation flow has been adapted to VHSIC hardware description language (VHDL). Details of the implementation strategy and performance gains achieved are reported.<
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