Providing a VHDL-interface for proof systems

When integrating formal methods into the design process, VHSIC hardware description language (VHDL) is unavoidable. A VHDL front end for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programs. Choosing a purely functional approach has the benefit that the generated programs can be animated. This improves the testability of the translator.<
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