Interconnect testing using BIST embedded in IEEE 1149.1 designs

As board and packaging techniques continue to drive to smaller geometries and increased densities, it becomes increasingly difficult to use conventional test techniques to test board interconnect and functionality. Fine-pitch QFPs, TAB packaging and multichip modules limit test accessibility and manufacturing defect detection. Of the typical faults found during manufacturing test of a board (opens, shorts, wrong parts, bad solder joints), over 50% can be traced to interconnect problems. These faults can be diagnosed using boundary scan test structures in much the same manner as probes are used on a traditional tester. This paper describes how a boundary scan design can easily be modified to include advanced test structures to regain controllability and observability of board interconnect.<
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