On clock routing for general cell layouts

Addresses the minimum-skew clock routing problem in general cell designs. The authors present a bottom-up construction method for clock distribution trees based on a generalized matching computation in channel intersection graphs. The clock routing trees produced by their method attain almost zero skew with only modest wirelength penalty. Experimental results show that clock skew of their routing tree is no more than 2% of that of a minimum spanning tree, while on average the cost of the tree is only 50% more than that of a minimum spanning tree.<
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