Partitioning schemes for circuit simulation on a multiprocessor array

The factorization of sparse matrices is used in the inner loop of many engineering algorithms. including circuit simulation. This time consuming operation can be speeded up by utilizing multiprocessor architectures. Distributed memory architectures can overcome the memory bottleneck normally associated with shared memory machines but require a careful distribution of matrix data to the processors. The authors present partitioning schemes that distribute the rows of the matrix to processors to allow a better utilization of the processing resources. They also present bounds on the speedup achieveable with partitioned matrices. They demonstrate that a good partitioning strategy coupled with more sophisticated scheduling algorithms improves the overall processor utilization.<
>