High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation

Quarter-micron Si/sub 1-x/Ge/sub x/ p-MOS devices with either thermal or PECVD oxides have been fabricated using an integrable process module (LOCOS isolation, threshold and deep well implants, p/sup +/ polysilicon gates, and TiSi/sub 2/) compatible with conventional 0.25 mu m CMOS with the Si/sub 1-x/Ge/sub x/ channel and Si cap deposited by selective UHV-CVD. Improvements in mobility and transconductance over deep submicron (0.25 mu m channel length) state-of-the-art Si p-MOSFETs were demonstrated by using silicon-germanium channels with low (10-25%) germanium content, both at room temperature (300 K) and low temperature (82 K). The use of Si/sub 1-x/Ge/sub x/ channels can provide better device performance in the same technology generation (same lithography, junction depth, etc.) and also help compensate for the external parasitic resistance penalty.<
>