16 Mbit SRAM cell technologies for 2.0 V operation

Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability.<
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