A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs

The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator) MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed. Since the ultra-thin SOI structure provides high noise immunity, the storage node capacitance can be reduced by more than 50%. Therefore, in the proposed DRAM cell a large storage capacitor need not be essential, and this will extend the DRAMs miniaturization to the gigabit levels. The cell structure schematic is shown and threshold voltage dependences on channel length of DELTA-, conventional NMOS-, and PMOS-FETs are demonstrated. DELTA shows good short channel characteristics compared to conventional NMOS.<
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