Small geometry SOI CMOS cell technology for high density SRAMs

The authors report on a full CMOS 4 M SRAM (static RAM) cell using bonded SOI (silicon-on-insulator). The cell area is 21.15 mu m/sup 2/ and the chip area is 129.9 mm/sup 2/. The cell layout is shown, and the cell transfer curves at a Vdd of 1.5 V and 3.3 V are presented. A sufficient noise margin is achieved even at a Vdd of 1.5 V, which is specific to CMOS cells.<
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