Hot carrier induced degradation in polycrystalline silicon TFTs: experimental and theoretical analysis

The application of bias-stresses with high source-drain voltage and different gate voltages produces in polycrystalline silicon thin-film transistors marked modifications both in the off-current as well as in the device transconductance. These effects have been explained in terms of hot-carrier effects related to a combination of charge injection into the gate insulator and formation of interface states near the drain.<
>