Median filter architecture based on sorting networks

The authors present a sorting-network-based architecture for computing two-dimensional median filters in real-time. The median computing network is a modified version of Batcher's sorting network with compare-swap units which sort 2 elements (sort-2) as well as 3 elements (sort-3) in 1 time unit. Introduction of sort-3 units reduces the latency of the network without loss of regularity. A (3*3) median filter has been implemented in 2- mu m CMOS using this approach. The architecture is completely pipelined and operates in the bit-serial mode with 8-b precision. The operating speed is 40 MHz.<
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