A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture

Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit.<
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