New decoding architecture to reduce peak current and its implementation to 4 M ECL SRAM

The authors describe the multitiming buffering architecture (MTBA) and the pseudo hierarchical word decoding architecture (pseudo-HWD). These architectures have been implemented on a 4M emitter-coupled logic (ECL) SRAM with a 0.6- mu m BiCMOS process, and have effectively reduced the peak current of the decoding circuit by 32% and maximum di/dt by 63%, as compared with the three-level HWD. The SRAM achieved a 7-ns access time and a 160-mA active current at 50 MHz.<
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