Performance evaluation of an event-driven logic simulation machine

The author evaluates the performance of an event-driven logic simulation machine, called the SP. Since an event-driven machine only schedules gates that have signal-changes on their inputs, it processes fewer gates than the level-sort machine does. However, if the event-driven machine spends too many clocks on dynamic scheduling, the simulation time cannot be reduced. The overhead for dynamic scheduling was measured, and it was found that it only averaged 2% over the total process. The evaluation was done by using the ISCAS89 benchmark circuits, and the results are shown on a machine cycle basis. Some special functions of the SP for acceleration were individually evaluated. The simulation speed was compared with that of a software simulator that used the same data structure and algorithm as the SP.<
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