A simple scheme for slot reuse without latency for a dual bus configuration

A simple scheme for slot reuse without latency for the dual bus configuration is studied. The scheme relies on information read in the previous slot and will be referred to as previous slot information (PSI) slot reuse. The scheme requires a minimal addition to the station hardware and its reliability is high. The efficiency of PSI is checked over a wide range of parameters and is found to be almost as good as destination release. The scheme can be implemented with or without the addition of erasure nodes.<
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