A large-grain data flow architecture utilizing multiple levels of parallelism

A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<
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