Optimized silicon-rich oxide (SRO) deposition process for 5 V only flash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO/sub 2/ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO/sub 2/ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm/sup 2/ at J=0.1 A/cm/sup 2/. The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices.<
>