Multibit decoding/encoding of binary codes using memory based architectures

The authors present new memory based architectures for the design of special purpose hardware for real-time compression and decompression of data. The decode/encode tree of any binary code is mapped on to a memory device that corresponds to simultaneous decoding/encoding of multiple bits. The hardware is programmable and adaptable and yields a high compression rate. Using 1 mu m CMOS process technology, this could lead easily to over 100 Mbit/s compression rate for the JPEG baseline compression scheme. Associated with the memory map, a new binary string alignment problem called the contiguous binary superstring is formulated and a heuristic algorithm is developed to solve it. An efficient algorithm for this problem is posed as an open question.<>